DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 641

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
19.3.1
HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits
that determine pin output and the internal state of the LPC interface, and status flags that monitor
the internal state of the LPC interface.
• HICR0
Bit
7
6
5
Bit Name
LPC3E
LPC2E
LPC1E
Host Interface Control Registers 0 and 1 (HICR0 and HICR1)
Initial
Value
0
0
0
Slave Host Description
R/W
R/W
R/W
R/W
LPC Enables 3 to 1
Enable or disable the LPC interface function. When the
LPC interface is enabled (one of the three bits is set to
1), processing for data transfer between the slave (this
LSI) and the host is performed using pins LAD3 to
LAD0, LFRAME, LRESET, LCLK, SERIRQ, CLKRUN,
and LPCPD.
0: LPC channel 3 operation is disabled
1: LPC channel 3 operation is enabled
0: LPC channel 2 operation is disabled
1: LPC channel 2 operation is enabled
0: LPC channel 1 operation is disabled
1: LPC channel 1 operation is enabled
LPC3E
No address (LADR3) matches for IDR3, ODR3,
STR3, or TWR0 to TWR15
LPC2E
No address (LADR2) matches for IDR2, ODR2, or
STR2
LPC1E
No address (LADR1) matches for IDR1, ODR1, or
STR1
Rev. 3.00 Sep. 28, 2009 Page 595 of 910
Section 19 LPC Interface (LPC)
REJ09B0350-0300

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