DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 622

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 Keyboard Buffer Control Unit (PS2)
18.4.3
This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard
side) in the event of a protocol error, etc. In this case, the system holds the clock low. During
reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when
the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is
an abort request from the system, and data transmission from the keyboard is aborted. Thus the
system can abort reception by holding the clock low for a certain period. A sample receive abort
processing flowchart is shown in figure 18.7, and the receive abort timing in figure 18.8.
Rev. 3.00 Sep. 28, 2009 Page 576 of 910
REJ09B0350-0300
(pin state)
(pin state)
(output)
(input)
KCLK
KCLK
KCLK
KBTE
KTER
KBTS
KD
Receive Abort
[1] to [3]
I/O inhibit
I/O inhibit
[4]
[5]
[6] [7] [8]
Start bit
1
0
Figure 18.6 Transmit Timing
2
1
8
7
9
Parity
10
Stop bit
notification
completed
Receive
11
[9] [10]
[11]