DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 585

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Figure 17.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)
12. Clear the IRIC flag to 0.
User processing
(master output)
(master output)
(slave output)
Note:* Data write
Write 0 to ACKE in ICCR, to clear received ACKB contents to 0.
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
ICDRE
ICDRS
ICDRT
SDA
IRTR
SDA
IRIC
SCL
in ICDR
prohibited
Start condition generation
[4] BBSY set to 1
SCP cleared to 0
(start condition issuance)
[5]
Interrupt
request
Address + R/W
Address + R/W
Bit 7
[6] ICDR write
1
Bit 6
2
Bit 5
Slave address
3
Bit 4
[6] IRIC clear
4
Bit 3
5
Bit 2
6
Rev. 3.00 Sep. 28, 2009 Page 539 of 910
Bit 1
7
[9] ICDR write
R/W
Section 17 I
Bit 0
8
[7]
A
9
Interrupt
request
2
C Bus Interface (IIC)
REJ09B0350-0300
[9] IRIC clear
Data 1
Bit 7
Data 1
1
Data 1
Bit 6
2

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