DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 846

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 25 List of Registers
Rev. 3.00 Sep. 28, 2009 Page 800 of 910
REJ09B0350-0300
Register Name
Port 2 data direction register
Port 1 data register
Port 2 data register
Port 3 data direction register
Port 4 data direction register
Port 3 data register
Port 4 data register
Port 5 data direction register
Port 6 data direction register
Port 5 data register
Port 6 data register
Port B output data register
Port 8 data direction register
Port B input data register
Port 7 input data register
Port B data direction register
Port 8 data register
Port 9 data direction register
Port 9 data register
Abbreviation
P2DDR
P1DR
P2DR
P3DDR
P4DDR
P3DR
P4DR
P5DDR
P6DDR
P5DR
P6DR
PBODR
P8DDR
PBPIN
P7PIN
PBDDR
P8DR
P9DDR
P9DR
Number
of bits
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Address
H'FFB1
(PORTS = 0)
(PORTS = 0)
(PORTS = 0)
H'FFB4
(PORTS = 0)
H'FFB5
(PORTS = 0)
(PORTS = 0)
(PORTS = 0)
H'FFB8
(PORTS = 0)
H'FFB9
(PORTS = 0)
(PORTS = 0)
(PORTS = 0)
H'FFBC
(PORTS = 0)
H'FFBD (Write)
(PORTS = 0)
H'FFBD (Read)
(PORTS = 0)
H'FFBE (Read)
(PORTS = 0)
H'FFBE (Write)
(PORTS = 0)
(PORTS = 0)
H'FFC0
(PORTS = 0)
H'FFC1
(PORTS = 0)
H'FFB2
H'FFB3
H'FFB6
H'FFB7
H'FFBA
H'FFBB
H'FFBF
Module
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
Data
Width
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Access
States
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2