DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 591

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Figure 17.13 Sample Flowchart for Operations in Slave Receive Mode
Read AASX, AAS and ADZ in ICSR
No
No
No
Read ICDR, clear IRIC flag
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Set ACKB = 0 in ICSR
Set ACKB = 1 in ICSR
and TRS = 0 in ICCR
Slave receive mode
Read TRS in ICCR
Last reception?
and ADZ = 1?
Set MST = 0
ICDRF = 1?
Initialize IIC
Read ICDR
Read ICDR
ESTP = 1 or
STOP = 1?
IRIC = 1?
TRS = 1?
IRIC = 1?
IRIC = 1?
AAS = 1
End
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
[2] Read the receive data remaining unread.
[1] Initialization. Select slave receive mode.
[3] to [7] Wait for one byte to be received (slave address + R/W)
[10] Read the receive data. The first read is a dummy read.
[5] to [7] Wait for the reception to end.
[8] Clear IRIC flag
[8] Clear IRIC flag.
[9] Set acknowledge data for the last reception.
[10] Read the receive data.
[5] to [7] Wait for reception end.
[11] Detect stop condition.
[12] Check STOP bit.
[8] Clear IRIC flag.
[12] Clear IRIC flag.
Slave transmit mode
General call address processing
* Description omitted
Rev. 3.00 Sep. 28, 2009 Page 545 of 910
Section 17 I
2
C Bus Interface (IIC)
REJ09B0350-0300

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