DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 280

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 14-Bit PWM Timer (PWMX)
In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in
figure 9.7. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of
the base pulse duty cycle is 2/256 × (T).
Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the
location of base pulse No. 63 according to table 9.6. Thus, an additional pulse of 1/256 × (T) is to
be added to the base pulse.
However, when CFS = 0 (base cycle = resolution (T) × 64), the duty cycle of the base pulse is
determined by the upper six bits and the locations of the additional pulses by the subsequent eight
bits with a method similar to as above.
Rev. 3.00 Sep. 28, 2009 Page 234 of 910
REJ09B0350-0300
Figure 9.7 Output Waveform when DADR = H'0207 (OS = 1)
Base pulse
High width: 2/256 × (T)
Base cycle
No. 0
Base cycle
No. 1
1 conversion cycle
Base pulse
2/256 × (T)
Additional pulse output location
Additional pulse
1/256 × (T)
Base cycle
No. 63