DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 556

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I
ICDRR and the ICDRF flag is set to 1. If ICDRR contains receive data that hasn’t been read out,
any further receive data is retained in ICDRS.
Since data are not transferred from ICDRS to ICDRR in transmit mode (TRS = 1), do not read
ICDRR in transmit mode (excluding the case where final receive data is read out in the
recommended operation flow of master receive mode).
If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data
and receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should
be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1.
ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value
of ICDR is undefined.
17.3.2
SAR sets the slave address and selects the communication format. If the LSI is in slave mode with
the I
upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device
specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to
0.
Rev. 3.00 Sep. 28, 2009 Page 510 of 910
REJ09B0350-0300
Bit
7
6
5
4
3
2
1
0
2
C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the
Bit Name
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
Slave Address Register (SAR)
2
C Bus Interface (IIC)
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Slave Address 6 to 0
Set a slave address.
Format Select
Selects the communication format together with the
FSX bit in SARX. See table 17.3.
This bit should be set to 0 when general call address
recognition is performed.