TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 116

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

(Value to be compared)
Match with TA0REG
Example: To output the following PWM waves on the TA1OUT pin at fc = 27 MHz:
TA01RUN
TA01MOD
TA0REG
TA1FFCR
P7CR
P7FC
TA01RUN
Register buffer
X: Don’t care, − : No change
overflow is detected when the TA0REG double buffer is enabled.
2
n
In this mode, the value of the register buffer will be shifted into TA0REG if 2
Use of the double buffer facilitates the handling of low duty ratio waves.
TA0REG
overflow
To achieve a 37.9-µs PWM cycle by setting φT1 to (2
Therefore n should be set to 7.
Since the low-level period is 15 µs when φT1
set the following value for TA0REG:
← –
← 1
← 0
← X
← X
← –
← 1
MSB
7
* Clock state
37.9 µs/ (2
15 µs/ (2
6
X
1
0
X
X
–
X
Figure 3.7.18 Register Buffer Operation
Up counter = Q
5
X
1
1
X
X
–
X
4
X
0
1
X
X
–
X
15.0 µ s
3
37.9 µ s
/fc) s ≈ 51 = 33H
3
3
–
–
0
1
–
–
–
/fc) s = 128 = 2
Q
Q
1
2
–
0
1
2
–
0
–
–
1
91C016-114
1
–
0
1
1
–
–
–
LSB
0
0
1
1
X
1
1
1
n
Stop TMRA0 and clear it to “0”.
Select 8-bit PWM mode (Cycle: 2
input clock.
Write 33H.
Clear TA1FF to “0”, enable the inversion and double buffer.
Set P70 and the TA1OUT pin.
Start TMRA0 counting.
Clock gear:
Shift into TA0REG
Up counter = Q
=
(2
Q
3
TA0REG (Register buffer)
write
2
/fc)s,
3
2
/fc) s (at fc = 27 MHz):
1/1
Q
3
7
) and select φ T1 as the
TMP91C016
2008-02-20
n