TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 164

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.10.1
Address
linked to CS3 of the CS/WAIT controller. The DRAM controller generates the DRAM access
cycle. The DRAM signals share pins with port 6 and port 7 (for details on setting the pins to
DRAM pins, see 3.5.4, Port 6 and 3.5.5 Port 7)
(1) Memory access control
Description of Operation
Row
TMP91C016 has a one-channel internal DRAM controller. This channel is normally
A10
A11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
in the CS/WAIT controller is accessed when access control is enabled, a valid signal is
output to DRAM in accordance with the DRAM memory access control register setting.
The access cycle (Bus cycle, number of waits) at this time depends on the
setting in the CS/WAIT controller.
bits, the specified area is accessed by the
<MACS> setting.
the rising of
pre-charge time (RAS high width). Slow access mode is set by DMEMCR<MACM>. A
reset clears <MACH> to 0 and sets NORMAL mode.
during the access cycle. The DMEMCR<MUXE> bit specifies whether or not to
multiplex addresses, and DMEMCR<MUX0:1> specifies the multiplexed address
width. Note, however, that the multiplexed address lines depend on the bus size: 8 bits
or 16 bits.
LCAS
Setting DMEMCR<MAC> to 1 enables access control. If the area set as the
If the bus size is 16-bits, the specified area is accessed using the
To facilitate the connection with low-speed DRAM, the DRAM controller accelerates
The internal address multiplexer outputs the row/column address from A0 to A11
Pin Name
P63 (
P74 (
P67 (
P66 (
P73 (
and
A10
A11
A12
A13
A14
A15
A8
A9
CS3
CAS
LCAS
UCAS
DRAMOE
8
−
−
−
−
Table 3.10.2 Address Multiplexing ( − : Don’t care)
8 Bits
WE
,
,
,
RAS
,
WE
LDS
UDS
), depending on the DMEMCR<MACS> setting. When the bus size is 8
RAS
,
A10
A11
A12
A13
A14
A15
A16
)
16
)
A9
EXRD
−
−
−
−
,
,
REFOUT
WE
signal when some waits are inserted, and extends the
,
Table 3.10.1 DRAM Pins
)
NMI
A10
A11
A12
A13
A14
A15
A16
A17
A9
)
8
)
−
−
−
91C016-162
9 Bits
Mode
Column Address
A10
A11
A12
A13
A14
A15
A16
A17
A18
16
−
−
−
RAS
REFOUT
DRAMOE
CAS
WE
8-Bit Bus
RAS
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
8
−
−
10 Bits
,
CAS
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
16
−
−
RAS
LCAS
UCAS
DRAMOE
WE
and
16-Bit Bus
WE
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
8
−
11 Bits
signals regardless of the
2CAS
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
16
−
TMP91C016
(
RAS
2008-02-20
Access bus size
(Set in the CS/WAIT
controller)
Multiplex
address length
CS3
CS3
,
UCAS
area
area
RAS