TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 131

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TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
Concurrent
Concurrent
Concurrent
with PC5
with PC5
with PC4
SCLK1
SCLK1
RXD1
f
φT0
SYS
I/O interface mode
SC1MOD0
<RXE>
φT0
φT2
φT8
φT32
RXDCLK
RB8
Serial clock generation circuit
<BR1CK1:0>
Receive buffer 1 (Shift register)
BR1CR
2
Receive buffer 2 (SC1BUF)
(UART only ÷ 16)
φT2
4
Prescaler
Receive
Receive
Figure 3.9.3 Block Diagram of the Serial Channel 1 (SIO1)
counter
control
<BR1S3:0>
8
BR1CR
φT8 φT32
16 32 64
Baud rate
generator
<BR1ADDE>
BR1CR
<BR1K3:0>
BR1ADD
<OERR><PERR><FERR>
SC1MOD0
<WU>
<PE>
Internal data bus
Parity control
SC1CR
Error flag
÷2
SC1CR
Serial channel
interrupt
control
91C016-129
<EVEN>
(from TMRA0)
TA0TRG
SC1MOD0
<SC1:0>
SC1CR
<IOC>
I/O
interface mode
UART
mode
SC1MOD0
TXDCLK
<SM1:0>
TB8
Transmission buffer (SC1BUF)
(UART only ÷ 16)
Transmission
Transmission
SIOCLK
counter
control
SC1MOD0
<CTSE>
INT request
INTRX1
INTTX1
TMP91C016
2008-02-20
Concurrent
with PC5
TXD1
Concurrent
with PC3
CTS1

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