TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 6

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

REFOUT
TA1OUT/SCOUT (P70)
WE
DRAMOE
SCLK1/
/
/
UCAS
LCAS
VLDVCC, GND
DLEBCD (PD3)
D1BSCP (PD0)
OPTRX0 (P72)
OPTTX0 (P71)
DOFFB (PD4)
D3BFR (PD2)
D2BLP (PD1)
(PB0 to PB2)
RXD1 (PC4)
/
TXD1 (PC3)
CTS1
/
/
EXRD
UDS
RAS
LDS
VLD0,1,2
VREF
(PC5)
(P67)
(P66)
(P73)
(P63)
SIO/UART/IrDA
VLD0 to VLD2
(Detecter)
8-bit timer
8-bit timer
8-bit timer
8-bit timer
SIO/UART
(TMRA0)
(TMRA1)
(TMRA2)
(TMRA3)
controller
Figure 1.1 TMP91C016 Block Diagram
(SIO1)
DRAMC
(SIO0)
Port B
Port C
Port D
Port 6
Port 7
Port 9
LCD
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
CPU (TLCS-900/L1)
(Watchdog
conversion
91C016-4
timer)
WDT
HVC
SR
32 bits
PC
W A
B C
D E
H L
IZ
SP
IX
IY
F
Clock doubler
Clock gear,
Keyboard
alarm-out
(4 blocks)
CS/WAIT
controller
controller
Melody/
Interrupt
H-OSC
L-OSC
MMU
input
RTC
Port 1
Port 2
Port 5
( ): Initial function after reset
EA24,
EA25,
(P60 to P63)
DVCC [3]
DVSS [3]
X1
X2
EMU0
EMU1
XT1 (PC6)
XT2 (PC7)
AM0
AM1
D0
A0
A8
P10~P17 (D8
P20
ALARM
EXWR
CS2D
CS2E
INT0 to INT2,INT3
(PB3 to PB5, P52)
KI0 to KI7 (P90 to P97)
MLDALM(PD7)
RESET
CS0
RD
HWR
R
WR
WAIT
NMI
/
to
to
to
W
to
(P74)
(LCLK0) to
A7
A15
D7
(P52)
(P56)
(P53)
(P72)
P27 (A16
CS2B
CS2C
(P71)
,
(P53)
MLDALM
to
MSK
EXWR
(P64),
(LCLK2)
D15)
to
CS3
A23)
(PD6)
TMP91C016
/
CS2A
VEECLK
2008-02-20
(P65),