TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 240

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TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
Note: Since the CPU accesses the internal area to read data from a port, the control signals of external
EA24 to EA25,
(3) Read cycle
RD
pins such as
regarded as depicting internal operation. Please also note that the timing and AC characteristics of
port input/output shown above are typical representation. For details, contact your local Toshiba
sales representative.
UDS LDS
D0 to D15
A23 to A0
Port input
SR_mode
,
WAIT
f
R/
(Note)
FPH
CSn
RD
W
RD
and
t
FPH
t
t
AC
AC
CS
are not enabled. Therefore, the above waveform diagram should be
t
t
t
AW
APH
t
APH2
AD
91C016-238
t
RD
t
t
t
RD
RR
RR
t
CW
D0 to D15
t
t
t
HR
CAR
CAR
TMP91C016
2008-02-20

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