TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 75

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.5.7
Port B (PB0 to PB5)
(VLD0 to VLD2), external interrupt input function (INT0 to INT2). It can be controlled by
IIMC register’s setting to select of rise up/fall down for interruption.
can set pull-up resistor to port B0 to B3, pull-up/pull-down register to port B4, B5. Selection
of pull-up or pull-down, is set by writing 1 corresponding bit of PBUDE register.
resistor. Only port B3 become to input with pull-up resistor by reset operation.
(1) PB0 to PB2 (VLD0 to VLD2)
Port B is 6-bit general-purpose I/O port. This I/O port have voltage level detector function
External interrupt function is set by writing to 1 correspond bit of PBFC register. And it
Resetting resets to PBCR, PBFC, PBUDE register, port B0 to B2, B4, B5 input without
Reset
Direction control
(on bit basis)
PB write
Pull-up resistor
Output
(on bit basis)
latch
PBUDE write
PBCR write
S
control
Voltage level detector input
PB read
Figure 3.5.17 Port B0 to B2
VLD0
VLD1
VLD2
91C016-73
<VLDnUSE>
Y
Selector
0
1
2
S B
A
P-ch (Programmable pull up)
PB0 (VLD0)
PB1 (VLD1)
PB2 (VLD2)
TMP91C016
2008-02-20