TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 195

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

LCDFFP
(0364H)
LCDCTL
(0363H)
3.13.4.2 Settlement to frame frequency function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Example1: In the case where frame period is set to 72.10 Hz by 240 coms.
value set in f
usually outputs the signal inverts polarity every frame period.
setting mentioned before. However this f
number, frame period can be corrected by increasing f
3.13.3.
Note: Please make the value set to f
(SR, RAM
mode)
0: OFF
1: ON
TMP91C016 defines so-called frame period (Refresh interval for LCD panel) by the
Basic frame period; DLEBCD signal, is made according to the resister f
The equation can calculate frame period.
Frame period = LCDCK/(D × f
Please select the value of f
DOFF
LCDON
R/W
FP7
7
7
0
COM(common number) ≤ f
Always
write 0
f
Therefore, LCDCTL<FP8> = 1 and LCDFFP<FP7:0> = 2FH are set up.
FP
FP
R/W
FP6
6
6
–
0
= 240 (COM) + 63 = 303 = 12FH (by Table 3.13.3)
[8:0]. DLEBCD pin outputs pulse every frame period. D3BFR pin
Always
write 0
R/W
FP5
5
5
–
0
LCDCTL Register
LCDFFP Register
91C016-193
FP
Data bus width
00: 8 bits (Byte mode)
01: 4 bits (
10: 1 bit (Bit mode)
Setting bit 7 to 0 for f
(SR mode)
FP
[8:0] as the frame period you want to set in the Table
BUS1
FP
R/W
FP4
4
0
4
) [Hz] D: constant for each common (Table 3.13.3)
≤ 320
FP
R/W
Nibble mode
[8:0] into the following range.
0
FP
FFP: setting of f
LCDCK: source clock of LCD
(Low clock is usually selected)
BUS0
R/W
FP3
[8:0] setting is generally equal to common
3
3
0
FP
)
Setting
direct
RAM
0: OFF
1: ON
MMULCD
R/W
FP2
2
0
FP
2
[8:0] with ease.
FP
Setting bit 8
for f
[8:0] resister
R/W
FP8
FP
FP1
1
0
1
Start
control
(SR mode)
0: Stop
1: Start
START
R/W
FP0
TMP91C016
0
0
0
2008-02-20
FP
[8:0]