TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 166

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.10.2
(3) DRAM initialization
Priorities
may overlap with DRAM read and write cycles. If an overlap occurs, the DRAM controller
gives priority to the cycle that started first. In case of CPU access first, refresh cycle occurs
after CPU access, and in case of refresh cycle first, DRAMC automatically insert to WAIT to
CPU until to finish that refresh cycle.
CAS
As the DRAM refresh cycle is asynchronous to the CPU operating cycle, the refresh cycle
HALT instruction (IDLE, STOP) while refreshing using the
refresh mode.
set DMEMCR<SRFC> to 0 to execute a single
the
mode starts. When the halt is released and the clock is supplied to the DRAM controller,
DMEMCR<SRFC> is automatically set to 1 and
released. After the release, be sure to execute a single
refresh to return to interval refresh mode. (Note that when a halt is released by a reset,
the I/O registers are initialized; therefore, the
executed.)
instruction, then execute a HALT instruction.
can not be moved. After reset,
mode on TMP91C016.
those pins.
required when using DRAM. Setting the DREFCR<DMI> bit to 1 generates the
dummy cycles. Dummy cycle generation is released by writing 0 to <DMI> (Including a
write due to reset), by enabling refresh cycle insertion (DREFCR<RC> = 1), or by
enabling access control (DMEMCR<MAC> = 1).
enabling access control, the <DMI> bit is not cleared to 0. The dummy cycle width is
fixed to 4 states; the interval, to 6 states.
CAS
-before-
This mode is used when the clock supplied to the DRAM controller is stopped by a
To refresh DRAM in
After setting DMEMCR<SRFC> to 0, execute any instruction, such as a NOP
In case of resetting release HALT condition, register is cleared, too, refresh operation
If it need data protection after reset condition, it need external pull-down resistor to
The DRAM controller can generate the continuous
When dummy cycle generation is released by enabling refresh cycle insertion or by
CAS
-before-
RAS
and
RAS
self-refresh mode
RAS
interval refresh mode. Then, before entering the HALT instruction,
pins maintain their low levels, and
CAS
91C016-164
-before-
RAS
and
RAS
CAS
self-refresh mode, first, set DRAM to
CAS
CAS
(
LCAS
CAS
-before-
-before-
-before-
,
CAS
UCAS
CAS
-before-
RAS
RAS
CAS
CAS
RAS
) pins become to High-Z
-before-
interval refresh. Then
interval refresh is not
-before-
-before-
self-refresh mode is
RAS
RAS
dummy cycles
TMP91C016
RAS
RAS
2008-02-20
self-refresh
interval
interval