TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 271

no-image

TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
Symbol
SC1BUF
SC1CR
BR1CR
MOD0
MOD1
ADD
SC1
BR1
SC1
(8-3) UART/SIO channel 1
UART/SIO channel (2/2)
Serial
channel 1
buffer
Serial
channel 1
control
Serial
channel 1
mode
Baud rate
control
Serial
channel 1
K setting
register
Serial
channel 1
mode1
Name
Address
(Prohibit
RMW)
20CH
20DH
20AH
20BH
208H
209H
Transmission
data bit8
Undefined
Receiving
data bit 8
Always
write 0
IDLE2
0: Stop
1: Run
RB7/TB7 RB6/TB6
I2S1
RB8
R/W
TB8
7
R
0
0
0
1: (16 − K)/16
BR1ADDE
Parity
0: Odd
1: Even
1: CTS
I/O
interface
mode
1: Full
0: Half
divded
enable
FDPX1
EVEN
CTSE
enable
duplex
duplex
R/W
6
0
0
0
0
R/W
91C016-269
1: Receive
RB5/TB5
1: Parity
00: φT0
01: φT2
10: φT8
11: φT32
BR1CK1
enable
enable
RXE
PE
5
0
0
0
R (Receiving)/W (Transmission)
1: Wake up
RB4/TB4
BR1CK0
Overrun
OERR
enable
WU
R (Cleared to 0 by reading)
4
0
0
0
Undefined
R/W
R/W
RB3/TB3
00: I/O Interface
01: UART 7 bits
10: UART 8 bits
11: UART 9 bits
1: Error
BR1S3
BR1K3
PERR
Parity
SM1
3
0
0
0
0
Setting the dividied frequency “N”
Sets the frequency divisor “K”
(Divided by N + (16 − K)/16)
RB2/TB2
Framing
BR1S2
BR1K2
FERR
SM0
2
0
0
0
0
(0 to F)
R/W
0: SCLK1↑
1: SCLK1↓
00: TA0TRG
01: Baud rate generator
10: Internal clock f
11: External clock SCLK1
RB1/TB1
SCLKS
BR1S1
BR1K1
SC1
1
0
0
0
0
TMP91C016
R/W
2008-02-20
1: SCLK1
RB0/TB0
BR1S0
BR1K0
Pin
SC0
IOC
0
0
0
0
SYS
0

Related parts for TMP91xy16FG