TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 188

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.13 LCD Driver Controller (LCDC)
LCD driver LSI.
driver in itself, and the other circuit handles a shift-register type LCD driver that must serially
transfer the display data to LCD driver for each display picture.
The TMP91C016 incorporates two types liquid crystal display driving circuit for controlling
One circuit handles a RAM build-in type LCD driver that can store display data in the LCD
Shift-register type LCD driver control mode (SR mode)
RAM built-in type LCD driver control mode (RAM mode)
Special mode
This section is constituted as follows.
control register before setting start register. After set start register LCDC outputs bus
release request to CPU and read data from source memory. After that LCDC transmits
data of volume of LCD size to external LCD driver through data bus. At this time, control
signals (DIBSCP etc.) connected LCD driver output specified waveform synchronize with
data transmission. After finish data transmission, LCDC cancels the bus release request
and CPU will re-start.
executed LCDC outputs chip select signal to LCD driver connected to the outside from
control pin (D1BSCP etc.). Therefore control of data transmission numbers corresponding
to LCD size is controlled by instruction of CPU.
(00E7hex). These bits are used when you want to operate LCDD and MELODY circuit
without low frequency clock (XTIN, XTOUT). After reset these two bits set to 0 and low
clock is supplied each LCDD and MELODY circuit. If you write these bits to 1, TA3
(Generate by timer 3) is supplied each LCDD and MELODY circuit. In this case, you should
set 32 kHz timer 3 frequency. For detail, look AC specification characteristics.
Set the mode of operation, start address of source data save memory and LCD size to
Data transmission to LCD driver is executed by move instruction of CPU.
After setting mode of operation to control register, when move instruction of CPU is
It is assigned <TA3LCDE> at bit0 and <TA3MLDE> at bit1, of EMCCR4 register
3.13.1
3.13.2
3.13.3
3.13.4
Feature of LCDC of Each Mode
Block Diagram
Control Registers
Operation Explanation of Each Mode
3.13.4.1
3.13.4.2
Shift-register Type LCD Driver Control Mode (SR mode)
RAM Built-in Type LCD Driver Control Mode (RAM mode)
91C016-186
TMP91C016
2008-02-20