TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 18

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TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
SYSCR0
(00E0H)
SYSCR1
(00E1H)
SYSCR2
(00E2H)
VLDCTL
(0449H)
3.3.2
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Note1: SYSCR1<bit7:4>,SYSCR2<bit7> are read as undefined value.
Note2: By reset, low-frequency oscillator become to enable condition.
SFRs
High-
frequency
oscillator (fc)
0: Stop
1: Oscillation
XEN
7
7
7
1
Low-
frequency
oscillator (fs)
0: Stop
1: Oscillation
0:
1: f
SCOSEL
fs
XTEN
FPH
R/W
6
6
6
1
0
Figure 3.3.3 SFR for System Clock
High-
frequency
oscillator (fc)
after release
of STOP
mode
0: Stop
1: Oscillation
Warm-up timer
00: Reserved
01: 2
10: 2
11: 2
WUPTM1
RXEN
R/W
8
14
16
5
5
5
/inputted frequency
1
1
91C016-16
Low-
frequency
oscillator (fs)
after release
of STOP
mode
0: Stop
1: Oscillation
WUPTM0
RXTEN
R/W
4
4
4
0
0
R/W
Selects clock
after release
of STOP
mode
0: fc
1: fs
Select
system clock
0: fc
1: fs
HALT mode
00: Reserved
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
0: Vcc
1: Vref
RSYSCK
XT1VSEL
HALTM1
SYSCK
operation
operation
R/W
3
3
3
W
0
0
1
0
Warm-up
timer
0: Write
1: Write start
0: Read end
1: Read Do
Select gear value of high frequency (fc)
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
101: (Reserved)
110: (Reserved)
111: (Reserved)
0: VLD don’t
1: VLD use
VLD2VSE VLD1VSE VLD0VSE
HALTM0
GEAR2
Don’t care
timer
warm up
not end
warm up
use
WUEF
R/W
R/W
2
2
2
0
1
1
0
R/W
Select prescaler clock
00: f
01: Reserved
10: fc/16
11: Reserved
0:
1:
0: VLD don’t
1: VLD use
<DRVE>
mode
select
SELDRV
GEAR1
PRCK1
STOP
IDLE1
use
R/W
FPH
R/W
1
1
1
0
0
0
0
Pin state
control in
STOP/IDLE1
mode
0: I/O off
1: Remains
0: VLD don’t
1: VLD use
PRCK0
GEAR0
the state
before
HALT
use
DRVE
R/W
TMP91C016
R/W
0
0
0
0
0
0
2008-02-20
0

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