TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 238

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

4.3
No.
AC measuring conditions
Note: Symbol “x” in the above table means the period of clock “f
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
• Output level: High = 0.7 Vcc, Low = 0.3 Vcc, CL = 50 pF
• Input level: High = 0.9 Vcc, Low = 0.1 Vcc
f
A0 to A23 valid →
SR mode (LCDC DMA case: READ only)
A0 to A23 valid → D0 to D15 input
SR mode (LCDC DMA case)
SR mode (LCDC DMA case)
D0 to D15 valid →
D0 to D15 valid →
A0 to A23 valid →
SR mode (LCDC DMA case: READ only)
A0 to A23 valid → Port input
A0 to A23 valid → Port hold
A0 to A23 valid → Port valid
RD
DS
RD
RD
RD
DS
DS
RD
FPH
WR
WR
WR
AC Characteristics
(1) Vcc = 2.7 to 3.6 V
“f
high/low oscillator frequency.
/
rise → A0 to A23 hold
Low Width
rise → D0 to D15 hold
rise → A0 to A23 hold
fall → D0 to D15 input
low width
rise → D0 to A15 hold
SYS
period (= x)
rise → A0 to A23 hold
low width
rise → D0 to D15 hold
WR
fall →
” for CPU core. The period of f
Parameter
WAIT
RD
WAIT
DS
WR
/
hold
rise
WR
rise
input
fall
(1 + N) WAIT mode
(1 + N) WAIT mode
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
FPH
AC
CAR
CAW
AD
RD
RR
HR
WW
DW
WD
AW
CW
APH
APH2
APO
91C016-236
FPH
depends on the clock gear setting or the selection of
1.5x − 13
0.5x − 13
2.5x − 15
2.0x − 15
2.0x − 15
2.0x − 15
1.5x − 35
1.5x − 35
2.5x + 0
2.0x + 0
x − 23
x − 13
x − 13
x − 25
x − 25
Min
37.0
3.5x
0
Variable
3.5x − 24
2.5x − 24
2.0x − 24
3.5x − 60
3.5x − 89
3.5x + 60
31250
Max
FPH
”, it’s half period of the system clock
Min
37.0
f
129
14
32
24
24
77
59
59
59
20
20
12
12
92
74
FPH
5
0
= 27 MHz
Max
105
189
68
50
69
40
TMP91C016
2008-02-20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns