TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 63

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

P5
(000DH)
P5CR
(000AH)
P5FC
(000BH)
P5FC2
(000CH)
P5UDE
(000EH)
Note 1: Read-modify-write is prohibited for register P5CR, P5FC, P5FC2 and P5UDE.
Note 2: When P53 pin is used as a
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
010.
7
7
7
7
7
0: Port
1:
Logic
select
0: 1 CLK
1: 0 CLK
Pull-up
resistance
0: Disable
1: Enable
P56F2
P56C
P56U
P56F
R
P56
6
6
6
/
6
6
0
0
0
1
W
Figure 3.5.6 Registers for Port 5
Data from external port (Output latch register is set to 1)
WAIT
Port 5 Function Register 2
Port 5 Function Register
pin, set P5CR<P53C> to 0 and chip select/wait control register <BnW2:0> to
Port 5 Control Register
5
5
5
5
5
Port 5 UDE Register
0: Input
91C016-61
Port 5 Register
W
4
4
4
4
4
1: Output
R/W
W
W
W
0: Port
1:
Pull-up
resistance
0: Disable
1: Enable
EXWR
P53C
P53U
P53F
P53
3
3
0
3
0
3
3
1
0: Port
1:
0: <P52F>
1: INT3
Pull-up
resistance
0: Disable
1: Enable
UDEP52
P52F2
HWR
P52C
P52F
P52
2
2
0
2
0
2
0
2
1
0: Pull up
1: Pull down
P52UD
1
1
1
1
1
0
II/O setting
0 Input
1 Output
RDE
TMP91C016
0
0
0
0
0
2008-02-20