TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 32

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.3.7
Note: It is only self refresh mode of DRAM. It can’t move normal operation and interval refresh
Block
SYSCR2<HALTM1:0>
mode of DRAM.
CPU
I/O ports
TMRA
RTC, MLD
SIO
DRAMC
WDT
LCDC,
Interrupt controller
Standby Controller
(1) HALT modes
HALT Mode
IDLE1 or STOP mode depending on the contents of the SYSCR2<HALTM1:0> register.
When the HALT instruction is executed, the operating mode switches to IDLE2,
The subsequent actions performed in each mode are as follows:
a. IDLE2: Only the CPU HALTs.
b. IDLE1: Only the oscillator and the RTC (Real time clock) and MLD continue to
c. STOP: All internal circuits stop operating.
The operation of each of the different HALT modes is described in Table 3.3.4.
Table 3.3.3 SFR Seting Operation During IDLE2 Mode
TMRA01
TMRA23
SIO0
SIO1
WDT
Table 3.3.4 I/O Operation During HALT Modes
The internal I/O is available to select operation during IDLE2 mode. By
setting the following register.
Table 3.3.3 shows the registers of setting operation during IDLE2 mode.
operate.
Internal I/O
Keep the state when the HALT instruction.
executed.
Available to select
operation block
91C016-30
Operate
IDLE2
11
TA01RUN<I2TA01>
TA23RUN<I2TA23>
SC0MOD1<I2S0>
SC1MOD1<I2S1>
WDMOD<I2WDT>
SFR
Stop
Note: Operational available
See Table 3.3.7, Table 3.3.8 are
Operational
available
IDLE1
10
Stop
STOP
01
TMP91C016
2008-02-20