TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 9

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

2.2
D0 to D7
P10 to P17
D8 to D15
P20 to P27
A16 to A23
A8 to A15
A0 to A7
P52
P53
P56
P60
LCLK0
P61
CS2
P63
CS3
P64
EA24
P65
EA25
LCLK2
P66
P67
R
RD
INT3
EXWR
MSK
WR
HWR
WAIT
CS0
CS1
CS2A
RAS
CS2B
CS2C
VEECLK
UCAS
UDS
WE
LCAS
LDS
REFOUT
/
Pin Name
W
Pin Names and Functions
The names of the input/output pins and their functions are described below.
Number
of Pins
8
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data (Lower): Bits 0 to 7 of data bus
Port 1: I/O port that allows I/O to be selected at the bit level
Data (Upper): Bits 8 to15 of data bus
Port 2: Output port
Address: Bits 16 to 23 of address bus
Address: Bits 8 to 15 of address bus
Address: Bits 0 to 7 of address bus
Read: Strobe signal for reading external memory. P5 <RDE>=0, output RD
when reading internal area.
Write: Strobe signal for writing data to pins D0 to D7
Port 52: I/O port (with pull-up resistor)
High Write: Strobe signal for writing data to pins D8 to D15
Interrupt request pin 3: Interrupt request pin with programmable rising/falling
Port 53: I/O port (with pull-up resistor)
Wait: Pin used to request CPU bus wait ((1 + N) WAIT mode)
Ex write: Strobe signal for writing data for RAM
Port 56: I/O port (with pull-up resistor)
Read/write: 1 represents read or dummy cycle; 0 represents write cycle.
Request VEECLK clock for external LCD-driver.
Port 60: I/O port (with pull-up resistor)
Chip select 0: Outputs 0 when address is within specified address area.
Lcd CLK: Command controll C/S for S/R type lcdd.
Port 61: I/O port (with pull-up resistor)
Chip select 1: Outputs 0 when address is within specified address area
Chip select 2: Outputs 0 when address is within specified address area
Expand chip select: 2A: Outputs 0 when address is within specified address
Port 63: I/O port (with pull-up resistor)
Chip select 3: Outputs 0 when address is within specified address area
Row address strobe: RAS strobe row address area for DRAM
Port 64: I/O port (with pull-up resistor)
Chip select 24: Outputs 0 when address is within specified address area
Expand chip select 2B: Outputs 0 when address is within specified address
Port 65: I/O port (with pull-up resistor)
Chip select 25: Outputs 0 when address is within specified address area
Expand chip select 2C: Outputs 0 when address is within specified address
Lcd CLK: Command controll C/S for S/R type lcdd.
Pomp-up CLK for external LCD driver
Port 66: I/O port (with pull-up resistor)
Upper column address strobe: Upper CAS strobe for 2CAS type DRAM.
Upper data enable strobe
Write strobe for DRAM (only 8-bit access)
Port 67: I/O port (with pull-up resistor)
Lower column address strobe: Upper CAS strobe for 2CAS type DRAM.
Lower data enable strobe
Refresh cycle state singanl for DRAM (only 8-bit access)
(When used to the external 8-bit bus)
91C016-7
edge
area
area
area
Functions
TMP91C016
2008-02-20