TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 217

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TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
3.15 Voltage Level Detector
VLD0 (PB0)
VLDGND
VLDVCC
some voltage level and also have interrupt generator. These voltage level compare circuit
(Voltage detector) are included in this LSI.
level detector (VLD0 to VLD2).
VREF
This function has 3-channel input voltage and reference voltage. Each channel can set own
It shows Figure 3.15.1,Figure 3.15.2 and Figure 3.15.3 block diagram of 3-channel voltage
These 3-channel VLD input can use also general purpose I/O port (Port B).
Figure 3.15.1 Block Diagram of Voltage Level Detector 0 (VLD0)
Devider select
control
Low/High
On/Off
91C016-215
<V0EN><LHSEL> <INT0EN> <VLD0IN> <V03:00>
VLD mode control resister0 VLDCR0
Resintance devider
Internal data bus
Comparator
+
Disable/Enable
Result
VLD0 compare
Interrupt request
control
TMP91C016
2008-02-20
INTVLD0

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