TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 224

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.15.2
Explanation of Function
Preferences
(1) Comparison reference voltage
(2) A selection of voltage level detector
(3) The voltage comparison start
3 bits of VLDCTR.
compare with the reference voltage and the voltage input from each VLD terminal.
Setting of detect level is decided by doing a partial pressure of the voltage input from
VLD terminal. And only VLD0 can set reference voltage to 0.9 V, and can compare the
voltage value too to 0.9 V to 1.4 V.
circuit and a switch between VLDGND by writing in 0 at each VLDCR* <V*EN> bit.
And, if it start from disable condition of VLD circuit, it must need first write <V*EN>
to 1 and next wait about 1ms set-up time (no-related with system clock frequency) and
next write VLDCR* <INT*EN> to 1, or first read VLDCR* <VLD*IN> data and use of
detect result.
detection level by a purpose of use.
establishing 1 in VLDCR* <V*EN>. VLDCR* <INT*EN> can know comparison result
afterwards after) progress more than (1mS between fixed time whether I establish 1
and wait for the interrupt input by leading VLDCR* <VLD*IN>.
than detect level that established it once, and having detect the voltage fall. It
establish 0 → 1 in VLDCR* <INT*EN> when let interrupt reflect the next comparison
update result, and update becomes possible in clearing current maintenance result. It
need to check result by all means when do not clear detect level and need to confirm
current search result. In particular VLDCR* <INT*EN> establishes 1 already, and
interrupt does not occur when detecting the voltage fall from starting detection when
does not execute the above-mentioned clear (0: Off → 1: On light of interrupt flag) once.
It select that does not use whether PB port is used as VLD with a register of low rank
Firstly, It supplies on VREF pin 1.5 V, reference voltage. Each voltage level detector
It can OFF with detector about the voltage comparison device and resistor divider
* (Asterisk) shows 0, 1 and 2 (3 channels)
A selection of three voltage level detector is different from next setting voltage
Main battery voltage detection (VLDCR0<V0EN> = 1)
Sub-battery voltage detection for back-up (VLDCR1<V1EN> = 1)
CPU-power source battery (VLDCR2<V2EN> = 1)
At first, It set detect level of VLD, and movement starts the voltage comparison by
It maintain the result by the comparison result control circuit after I became less
* (Asterisk) shows 0, 1 and 2 (3 channels)
level is possible by 0.1 V step.
level is possible by 0.1 V step.
Detection voltage range is 0.9 V to 2.6 V. The voltage comparison of totaled 18
Detection voltage range is 2.2 V to 2.6 V. The voltage comparison of totaled 5
Detection voltage points are 1.7 V, 2.6 V and 2.9 V.
91C016-222
TMP91C016
2008-02-20