TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 130

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TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
Concurrent
OPTRX0
with P72
select
IrDA
CLK
3.9.1
f
φT0
SYS
SC0MOD0
<RXE>
φT0
φT2
φT8
φT32
Block Diagrams
RXDCLK
RB8
Figure 3.9.2 is a block diagram representing serial channel 0.
Serial clock generation circuit
Receive buffer 1 (Shift register)
<BR0CK1:0>
BR0CR
2
Receive buffer 2 (SC0BUF)
(UART only ÷ 16)
φT2
4
Prescaler
Receive
Receive
Figure 3.9.2 Block Diagram of the Serial Channel 0 (SIO0)
counter
control
8
<BR0S3:0>
φT8 φT32
BR0CR
16 32 64
Baud rate
generator
<BR0ADDE>
BR0CR
<BR0K3:0>
<OERR><PERR><FERR>
SC0MOD0
<WU>
BR0ADD
<PE>
Internal data bus
Parity control
SC0CR
Error flag
SC0CR
Serial channel
interrupt
control
91C016-128
<EVEN>
(from TMRA0)
TA0TRG
SC0MOD0
<SC1:0>
UART
mode
TXDCLK
TB8
Transmission buffer (SC0BUF)
(UART only ÷ 16)
Transmission
Transmission
SIOCLK
counter
control
INT request
INTRX0
INTTX0
TMP91C016
2008-02-20
OPTTX0
Concurrent
with P71

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