TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 61

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.5.3
Port 5 (P52, P53, P56)
P5CR, P5FC, P5FC2 and P5UDE. And P52 port have
have
function.
P5FC2 to 0. And sets P52, P53, P56 to input mode with pull-up resistor.
the CPU’s control/status signal.
static RAM) of the
is accessed.
Port 5 is an 3-bit general-purpose I/O port. This I/O port is set using control register
Resetting resets all bits of P5 and bit 3, 5 of P5UDE to 1, all bits of P5CR, P5FC and
In addition to functioning as a general-purpose I/O port, Port 5 also functions as I/O for
When the P5<RDE> register clearing to 0, outputs the
If the <RDE> remains 1, the
WAIT
input,
control (on bit basis)
Function control2
P5UDE write
Direction control
Function control
P5FC2 write
Pull-up resistor
P5FC write
(on bit basis)
P5CR write
(on bit basis)
(on bit basis)
P5 write
Reset
Output
latch
RD
EXWR
S
pin even when the internal addressed.
Figure 3.5.4 Port 5 (P52)
output, P56 port have R/W output, MSK input, except port
INT3
HWR
P5UDE<UDE52>
P5UDE<P52UD>
A
B
RD
91C016-59
strobe signal is output only when the external address
S
P5 read
Rise up/fall down
edge detect
Output buffer
HWR
IIMC<I3EDGE>
RD
output, INT2 input, P53 port
strobe (used for the peused
P-ch (Programmable pull up)
N-ch (Programmable pull down)
P52 (
HWR
TMP91C016
2008-02-20
, INT3)