TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 162

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TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
DREFCR
(0430H)
Bit symbol
Read/Write
After reset
Function
Dummy
cycle
0: Disable
1: Dummy
cycle
DMI
7
0
Refresh cycle insertion interval
RS2
Figure 3.10.1 Refresh Control Register
6
0
000: 31 states
001: 110 states
010: 220 states
011: 450 states
100: 900 states
101: 1200 states
110: 1800 states
111: 2700 states
DREFCR1 Register
RS1
5
0
91C016-160
RW2
RS0
4
0
0
0
0
0
1
1
1
1
R/W
See Table 3.10.3 “Refresh Cycle Insertion Intervals”
Refresh cycle width control
RW1
0
0
1
1
0
0
1
1
RW2
3
0
Refresh cycle width
RW0
0
1
0
1
0
1
0
1
Refresh cycle control
Dummy cycle control
000: 2 states
001: 3 states
010: 4 states
011: 5 states
100: 6 states
101: 7 states
110: 8 states
111: 9 states
0
1
0
1
RW1
2
0
No refresh cycle
Refresh cycle
No dummy cycle
Dummy cycle
Refresh cycle width
RW1
2 states
3 states
4 states
5 states
6 states
7 states
8 states
9 states
1
0
Refresh
cycle
0: Disable
1: Enable
TMP91C016
RC
0
2008-02-20
0

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