TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 169

no-image

TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
WDT counter
WDT interrupt
WDT clear
(Software)
WDT counter
WDT interrupt
Internal reset
(f
f
device. In this case, the reset time will be between 22 and 29 states (26.1 to 34.4 µs at f
= 1 state )is f
(f
SYS
SYS
OSCH
The watchdog timer consists of a 22-stage binary counter which uses the system clock
The runaway is detected when an overflow occurs, and the watchdog timer can reset
/2
) as the input clock. The binary counter can output f
21
) by sixteen through the clock gear function.
.
n
n
FPH
/2, where f
Overflow
Figure 3.11.2 NORMAL Mode
(26.1 to 34.4 µs at f
Figure 3.11.3 RESET Mode
FPH
Overflow
91C016-167
is generated by dividing the high-speed oscillator clock
22 to 29 states
OSCH
= 27 MHz, f
Write clear code
FPH
= 1.7 MHz)
SYS
/2
15
, f
SYS
/2
17
0
, f
TMP91C016
2008-02-20
SYS
/2
19
OSCH
and

Related parts for TMP91xy16FG