TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 120

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.8.1
Address
000000H
100000H
200000H
300000H
3D0000H
3E0000H
3F0000H
600000H
800000H
C00000H
FFFFFFH
3C0000H
400000H
E00000H
FFFF00H
Recommendable Memory Map
memory correspondence is shown in Figure 3.8.1. And, a physical-address map is shown in
Figure 3.8.2.
section of CS/WAIT controller. Setting of register in MMU is not necessary.
The recommendation logic address memory map at the time of varieties extension
However, when memory area is less than 16 Mbytes and is not expanded, please refer to
Since it is being fixed, the address of a local-area cannot be changed.
768 KB
Size
64 KB
64 KB
64 KB
64 KB
−256 B
1 MB
1 MB
1 MB
2 MB
2 MB
4 MB
2 MB
256 B
2 MB
Memory map
COMMON0
COMMON1
LOCAL3
COMMON2
Vector area
LOCAL2
LOCAL0
LOCAL1
BLANK
Figure 3.8.1 Logical Address Map
0
0
0
0
91C016-118
1
1
1
1
2
2
BANK
2
2
3
3
3
････
4
4
4
5
5
5
: Internal area
: Overlapped with common area
6
6
14 15
6
7
7
7
CS/WAIT
CS3
CS0
CSEX
CSEX
CSEX
CSEX
CSEX
CS1
CS2
CS2
CS
CS3
CS0
CS1
CS2B
CS2E
D1BSCP
D2BLP
D3BFR
DLEBCD
CS2C
CS2D
CS2A
None
(BANK0 to 3)
(BANK4 to 7)
(BANK8 to 11)
(BANK12 to 15)
TMP91C016
2008-02-20