TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 194

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.13.4
3.13.4.1 Shift-register Type LCD Driver Control Mode (SR mode)
Operation Explanation of Each Mode
control registers before setting start register. After set start register LCDC outputs
bus release request to CPU and read data from source memory. After that LCDC
transmits data of volume of LCD size to external LCD driver through data bus. At this
time, control signals (D1BSCP etc.) connected LCD driver output specified waveform
synchronize with data transmission. After finish data transmission, LCDC cancels the
bus release request and CPU will restart.
DLEBCD and D2BLP signal.
out
EMCCR0<TA3LCDE>. After reset, this bit is cleared to “0” and low frequency
oscillator is selected.
Figure 3.13.6, Figure 3.13.7.
number and CPU stop timer (t
(Frame frequency) by the common number is shown in Table 3.13.3 and Table 3.13.4.
is built into even when the command for LCDD is written (Read is prohibited). Please
refer to Figure 3.13.5. When these signals are outputted from CS0, set
P63FC3<P60F3>, and when these signals are outputted from CS2C, set
P6FC3<P65F3>. Please refer the section of “Port 6”.
Set the mode of operation, start address of source data save memory and LCD size to
LCD controller uses the clock (LCDCK) different from f
LCDCK can be selected from the low frequency oscillator (fs: 32.768kHz) or timer
LCDC timing figure in the case of 240 seg × 120 com and BYTE mode is shown in
The table of t
The example of a 240 seg × 120 com LCD connection circuit is shown Figure 3.13.8.
The circuit that can correspond without especially adding an external circuit outside
(TA3OUT)
LCLK mode (only write)
Note: When LCLK mode selected, CS signal out OR gate (Original CS signal and
Normal CS signal
signal). CS signal is not ouptut when read.
LP
outputs
A23 to A0
(D2BLP pin cycle) by the number of segments and the common
CLK
91C016-192
from
Address
STOP
internal
)/stop ratio are shown in Table 3.13.2 and f
8bit
timer
Address + 1
circuit
SYS
to make D3BFR,
(TMRA23)
TMP91C016
2008-02-20
WR
/ HWR
by
FP