TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 270

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

Symbol
Symbol
SC0BUF
SC0CR
BR0CR
MOD0
MOD1
SIRCR
ADD
SC0
BR0
SC0
(8) UART/SIO channel (1/2)
(8-1) UART/SIO channel 0
(8-2) IrDA
Serial
channel 0
buffer
Serial
channel 0
control
Serial
channel 0
mode0
Baud rate
control
Serial
channel 0
K setting
register
Serial
channel 0
mode1
IrDA
control
register
Name
Name Address
Address
(Prohibit
207H
RMW)
200H
201H
202H
203H
204H
205H
Transmission
pulse width
0: 3/16
1: 1/16
Undefined
Receiveing
data bit 8
Transfer
data bit 8
IDLE2
0: Stop
1: Run
PLSEL
RB7/TB7
R/W
Always
write 0
7
RB8
I2S0
R/W
0
TB8
7
R
0
−
0
0
Receiving
data
0: H pulse
1: L pulse
BR0ADDE
1: (16 − K)/16
1: Full
0: Half
Parity
0: Odd
1: Even
I/O
interface
RXSEL
RB6/TB6
divded
enable
FDPX0
Always
R/W
write 0
duplex
duplex
EVEN
R/W
6
0
6
0
0
0
0
-
R/W
91C016-268
Transmission
0: Disable
1: Enable
1: Parity
Receive
0: Receive
1: Receive
00: φT0
01: φT2
10: φT8
11: φT32
RB5/TB5
BR0CK1
TXEN
R/W
enable
function
disable
enable
RXE
5
0
PE
5
0
0
R (Receiving)/W (Transmission)
0
Receiving
0: Disable
1: Enable
RB4/TB4
BR0CK0
Overrun
RXEN
Always
write 0
OERR
R/W
R (Cleared to 0 by reading)
4
0
4
0
0
-
Undefined
R/W
R/W
Set effective SIRRxD pulse width
Pulse width more than 2x × (Set value + 1) +
100ns
Possibale: 1 to 14
Impossible: 0, 15
00: I/O Interface
01: UART 7 bits
10: UART 8 bits
11: UART 9 bits
SIRWD3
RB3/TB3
1: Error
BR0S3
BR0K3
PERR
Parity
SM1
3
0
3
0
0
0
0
Setting the dividied frequency “N”
Sets the frequency divisor “K”
(Divided by N + (16 − K)/16)
RB2/TB2
SIRWD2
Framing
BR0S2
BR0K2
FERR
SM0
2
2
0
0
0
0
0
(0 to F)
R/W
R/W
00: TA0TRG
01: Baud rate generater
10: Internal clock f
11: IrDA clock
RB1/TB1
SIRWD1
BR0S1
BR0K1
SC1
1
0
0
0
1
0
TMP91C016
2008-02-20
0
RB0/TB0
SIRWD0
BR0S0
BR0K0
SC0
SYS
0
0
0
0
0