TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 161

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.10 DRAM Controller
The DRAM controller consists of a control circuit to refresh the DRAM, an access circuit for
reading and writing, and a row/column address multiplexer.
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TMP91C016 incorporates a 1-channel DRAM controller for interface with × 8-/16-bit DRAM.
Refresh mode
Refresh interval
Programmable (31 to 2700 states)
Refresh cycle width
Programmable (2 to 9 states)
Mapping areas
Address mapping size
Memory access mode
2CAS mode
Memory access address length
8 to 11 bits selectable
Wait control
In according with CS/WAIT controller setting
Arbitration of refresh/access contention
Refresh has higher priority. Wait states are automatically inserted in the access cycle.
CAS
CS3
CS3
area
areas: 32 kbytes-8 Mbytes
before
RAS
refreshing
91C016-159
TMP91C016
2008-02-20