TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 34

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

♦ : After clearing the HALT mode CPU starts interrupt processing.
○: After clearing the HALT mode CPU resumes executing starting from instruction following the HALT
× : It can not be used to release the HALT mode.
− : The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level.
* 1: Releasing the HALT mode is executed after passing the warm-up time.
* 2: INTVLD0 to INTVLD2 are NMI (Non maskable interrupt) class in point of view from interrupt circuit, but
Note:
instruction.
There is not this combination type.
these signals are actually maskable signals. If you want to mask these signals, you can controll by VLD
circuit.
Status of Received Interrupt
Example: Clearing IDLE1 mode
When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status,
hold level H until starting interrupt processing. If level L is set before holding level L, interrupt
processing is correctly started.
NMI
INTWD
INT0 to INT3 (Note 1)
INTALM0 to INTALM4
INTTA0 to INTTA3
INTRX0 to INTRX1, TX0 to TX1
INTKEY
INTRTC
INTLCD
INTVLD0 to INTVLD2
RESET
An INT0 interrupt clears the halt state when the device is in IDLE1 mode.
HALT mode
Address
8200H
8203H
8206H
8209H
820BH
820EH
820FH
Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation
INT0
LD
LD
LD
EI
LD
HALT
LD
*2
(IIMC), 00H
(INTE0), 06H
5
(SYSCR2), 28H
XX, XX
(PBFC), 08H
(Interrupt level) ≥ (Interrupt mask)
IDLE2
Interrupt Enabled
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
91C016-32
IDLE1 STOP
; Sets PB3 to INT0
; Selects INT0 interrupt rising edge.
; Sets INT0 interrupt level to 6.
; Sets interrupt level to 5 for CPU.
; Sets HALT mode to IDLE1 mode.
; HALTs CPU.
♦
♦
♦
♦
♦
♦
×
×
×
×
Reset initializes the LSI
♦
♦
♦
♦
×
×
×
×
×
×
*1
*1
*1
*1
(Interrupt level) < (Interrupt mask)
INT0 interrupt routine
IDLE2
○
○
○
○
Interrupt Disabled
−
−
×
×
×
−
RETI
IDLE1 STOP
○
○
○
○
−
−
×
×
×
−
TMP91C016
2008-02-20
○
○
−
−
×
×
×
×
×
−
*1
*1