TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 144

no-image

TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
(0209H)
SC1CR
Note: As all error flags are cleared after reading do not test only a single bit with a bit-testing instruction.
Bit symbol
Read/Write
After reset
Function
Received
data bit8
Undefined
RB8
7
R
Figure 3.9.10 Serial Control Register (SIO1, SC1CR)
Parity
0: Odd
1: Even
EVEN
6
0
R/W
Parity
addition
0: Disable
1: Enable
PE
5
0
91C016-142
Overrun
OERR
R (Cleared to 0 when read)
4
0
1: Error
PERR
Parity
0
3
I/O interface input clock select
Edge selection for SCKL pin (Input mode only)
Framing error flag
Parity error flag
Overrun error flag
0
1
0
1
Framing
Parity addition enable
Even parity addition/check
Received data bit8
FERR
0
1
0
1
2
0
Baud rate generator
SCLK1 pin input
Transmits and receives
data on rising edge of SCLK1.
Transmits and receives
data on falling edge of SCLK1.
Disabled
Enabled
Odd parity
Even parity
0: SCLK1
1: SCLK1
SCLKS
1
0
R/W
0: Baud rate
1: SCLK1
generator
pin input
Cleared to 0
when read
IOC
0
0
TMP91C016
2008-02-20

Related parts for TMP91xy16FG