TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 57

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

X: Don’t care
Note 1: Port1 is able to set port function or data bus by AM1, AM0 setting.
Note 2: If you want to use WAIT input, it needs BxCS register (1 + N) wait setting.
Note 3: In case of P76/MSK set MSK input, it can set logical selection by P7FC<P76F>.
Note 4: OPTRX0, OPTTX0, TXD1, RXD1, SCLK1,
Note 5: In case of P65F2D and P65F2, both write 1, it set P65F2D (VEECLK).
Note 6: Selection of
Note 7: Selection of
Note 8: Selection of
Note 9: Oscillator setting of XT1 and XT2 is controlled by SYSCR0<XTEN> and this control have priority
Note 10: Selection of
Note 11: Selection of
Note 12: If One of PB0 to PB2 is set VLD function, other PBx pin can’t output function even port function
Note 13: Selection of SCLK and
Note 14: Selection of
Port 9
Port B
Port C
Port D
Port
These pins can set input/output data’s logical selection by each Pn register.
over other setting.
setting. And these pin can only VLD input or port output. VLD function is set by
VLDCTL<VLD*USE>.
P90 to P97
PB0 to PB5
PB0
PB1
PB2
PB3
PB4
PB5
PC3 to PC5
PC6, PC7
PC3
PC4
PC5
PC6
PC7
PD0 to PD7
PD0
PD1
PD2
PD3
PD4
PD6
PD7
Pin Name
UCAS
LCAS
WE
CS0
CS2C
CS3
and
Input port
KI0 to KI7 input
Input port
Output port
VLD0 input (Note 12)
VLD1 input (Note 12)
VLD2 input (Note 12)
INT0 input
INT1 input
INT2 input
Input port
Output port
TXD1 output (Note 4)
RXD1 input (Note 4)
SCLK1 input (Note 4, 13)
SCLK1 output (Note 4, 13)
XT1 input (Note 9)
XT2 output (Note 9)
Input port
Output port
D1BSCP output
D2BLP output
D3BFR output
DLEBCD output
DOFFB output
MLDALM output
MLDALM
CTS1
ALARM
Table 3.5.3 I/O Registers and Specifications (2/2)
and LCLK is set by P6FC3<P60F3>.
and
and
and
and LCLK is set by P6FC3<P65F3>.
CAS
input (Note 4, 13)
RAS
output
CTS
REFOUT
WE
output
depend on CS/WAIT bus width control (8 bits or 16 bits).
Specification
is set by B3CS<B3OM1:0>.
depend on CS/WAIT bus width control (8 bits or 16 bits).
is set by SC1MOD0<CTSE>.
depend on CS/WAIT bus width control (8 bits or 16 bits).
91C016-55
CTS1
:
Pn
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
I/O Register Setting Data
PnCR
X
X
−
−
0
1
0
0
0
0
0
0
0
1
1
0
0
1
0
−
0
1
1
1
1
1
1
1
1
PnFC
0
1
0
0
−
−
−
1
1
1
0
0
1
−
0
1
0
X
X
0
0
1
1
1
1
1
1
1
1
PnFC2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
TMP91C016
2008-02-20
PnFC3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−