TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 165

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

RS2
0
0
0
0
1
1
1
1
Refresh Cycle
(2) Refresh control block
RS1
CAS
0
0
1
1
0
0
1
1
refreshing DRAM. When using an 8-bit bus, the device also outputs state signal
set by program, the DRAM refresh is easily realized. The refresh controller block has
the following features.
refresh mode vary according to the DRAM being used.
accordance with the system clock and type of DRAM used, by modifying the value of
the refresh control register.
REFOUT
a.
b.
c.
-before-
TMP91C016 outputs the
As the output cycle and pulse width of the
The refresh interval and the refresh cycle width in the
The refresh interval and the refresh cycle width in TMP91C016 can be set in
•
•
•
•
•
Refresh cycle insertion interval
accordance with the system clock used.
Refresh cycle width
Refresh cycle control
refresh cycle.
CAS
RS0
3 bits of the DREFCR<RS2:0> register is used to set insertion interval in
Example: When using the system clock at 25 MHz, set these bits to 111 to set
3 bits of the DREFCR<RW2:0> register can vary the refresh cycle width (
Manipulating the bits of the DREFCR<RC> register enables or disables the
0
1
0
1
0
1
0
1
Refresh interval: 31 to 2700 states (Programmable)
Refresh cycle width: 2 to 9 states (Programmable)
Dummy cycles can be generated.
The refresh cycle is asynchronous the CPU operating cycle.
RAS
Refresh mode:
, low output width).
to indicate a refresh cycle.
Table 3.10.3 Refresh Cycle Insertion Interval
Insertion
interval refresh mode
(States)
Interval
1200
1800
2700
110
220
450
900
31
the DRAM refresh cycle to 216 µs.
self-refresh mode
CAS
112.5
225
300
450
675
8 MHz
27.5
55
7.55
91C016-163
RAS
-before-
,
10 MHz
180
240
360
540
CAS
22
44
90
6.2
RAS
(
LCAS
12.5 MHz
144
192
288
432
interval refresh mode,
17.6
35.2
72
Frequency (f
4.96
RAS
,
UCAS
,
14 MHz
128.6
171.4
257.1
385.7
CAS
15.7
31.4
64.3
4.43
) signals, which can be used for
OSCH
(
LCAS
16 MHz
112.5
150
225
337.5
13.75
27.5
56.25
CAS
3.88
)
,
UCAS
-before-
20 MHz
120
180
270
CAS
11
22
45
90
3.1
) output can be
TMP91C016
RAS
-before-
2008-02-20
(Unit: µs)
25 MHz
144
216
17.6
36
72
96
interval
2.48
8.80
RAS
RAS
,