TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 281

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

(2) Points to note
a)
b)
c)
d)
e)
f)
g)
h) CPU (Micro DMA)
i)
j)
k) Releasing the HALT mode by requesting an interruption
AM0 and AM1 pins
active.
EMU0and EMU1
Reserved address areas
HALT mode (IDLE1)
RTCCR<RTCRUN> to 0 stop the timer for the real-time clock before the HALT instructions
is executed.
Warm-up counter
an external oscillator. As a result a time equivalent to the warm-up time elapses between
input of the release request and output of the system clock.
Programmable pull-up resistance
are set for use as input ports. When the ports are set for use as output ports, they cannot be
turned ON/OFF by a program.
Consequently read-modify-write instructions are prohibited.
Watchdog timer
watchdog timer is not to be used, disable it.
in the CPU (e.g., the transfer source address register (DMASn)).
Undefined SFR
POP SR instruction
INT3, INTKEY, INTRTC, INTALM0 to INTALM4, INTVLD0 to INTVLD2) which can
release the HALT mode may not be able to do so if they are input during the period CPU is
shifting to the HALT mode (for about 5 clocks of f
not applicable to this case). (In this case, an interrupt request is kept on hold internally.)
status can be released without difficulty. The priority of this interrupt is compared with
that of the interrupt kept on hold internally, and the interrupt with higher priority is
handled first followed by the other interrupt.
This pin is connected to the VCC or the VSS pin. Do not alter the level when the pin is
Open pins.
The TMP91C016 does not have any reserved areas.
When IDLE1 mode is used (in which oscillator operation only occurs), set
The warm-up counter operates when STOP mode is released, even if the system is using
The programmable pull-up resistor can be turned ON/OFF by a program when the ports
The data registers (e.g., P5) are used to turn the pull-up/pull-down resistors on/off.
The watchdog timer starts operation immediately after a reset is released. When the
Only the LDC cr, r and LDC r, cr instructions can be used to access the control registers
The value of an undefined bit in an SFR is undefined when read.
Please execute the POP SR instruction during DI condition.
Usually, interrupts can release all halts status. However, the interrupts (
If another interrupt is generated after it has shifted to HALT mode completely, halt
91C016-279
FPH
) with IDLE1 or STOP mode (IDLE2 is
NMI
TMP91C016
2008-02-20
, INT0 to