TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 136

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

(3) Serial clock generation circuit
(4) Receiving counter
(5) Receiving control
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the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data; each
data bit is sampled three times – on the 7th, 8th and 9th clock cycles.
rule.
clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is
taken to be 0.
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This circuit generates the basic clock for transmitting and receiving data.
The receiving counter is a 4-bit binary counter used in UART mode which counts up
The value of the data bit is determined from these three samples using the majority
For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and 9th
In I/O interface mode
In UART mode
In I/O interface mode
In UART mode
generated by dividing the output of the baud rate generator by 2, as described
previously.
falling edge will be detected according to the setting of the SC1CR<SCLKS>
register to generate the basic clock.
clock, the internal system clock f
or the external clock (SCLK0) is used to generate the basic clock SIOCLK.
sampled on the rising or falling edge of the shift clock which is output on the
SCLK0 pin.
sampled on the rising or falling edge of the SCLK1 input, according to the
SC1CR<SCLKS> setting.
majority rule. Received bits are sampled three times; when two or more out of
three samples are 0, the bit is recognized as the start bit and the receiving
operation commences.
majority rule.
In SCLK output mode with the setting SC1CR<IOC> = 0, the basic clock is
In SCLK input mode with the setting SC1CR<IOC> = 1, the rising edge or
The SC1MOD0<SC1:0> setting determines whether the baud rate generator
In SCLK output mode with the setting SC1CR<IOC> = 0, the RXD1 signal is
In SCLK input mode with the setting SC1CR<IOC> = 1, the RXD1 signal is
The receiving control block has a circuit, which detects a start bit using the
The values of the data bits that are received are also determined using the
91C016-134
SYS
, the match detect signal from timer TMRA0
TMP91C016
2008-02-20