TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 92

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

Note: “xxxxx” indicates that the input data from these bits are ignored during a read. During a
Operand Data
Bus Width
16 bits
32 bits
8 bits
write, indicates that the bus for these bits goes to high-impedance; also, that the write
strobe signal for the bus remains inactive.
(1) Master enable bits
(2) Data bus width selection
master bit which is used to enable or disable settings for the corresponding address
area. Writing 1 to this bit enables the settings. Reset disables (Sets to 0) <B0E>,
<B1E> and <B3E>, and enabled (Sets to 1) <B2E>. This enables area is only CS2.
select/wait control register specifies the width of the data bus. This bit should be set to
0 when memory is to be accessed using a 16-bit data bus and to 1 when an 8-bit data
bus is to be used.
is known as “Dynamic bus sizing”. For details of this bus operation see Table 3.6.2.
Bit7 (<B0E>, <B1E>, <B2E> or <B3E>) of a chip select/wait control register is the
Bit3 (<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS> or <BEXBUS>) of a chip
This process of changing the data bus width according to the address being accessed
Operand Start
(Even number)
(Even number)
(Even number)
(Odd number)
(Odd number)
(Odd number)
Address
2n + 0
2n + 1
2n + 0
2n + 1
2n + 0
2n + 1
Table 3.6.2 Dynamic Bus Sizing
Memory Data
Bus Width
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
91C016-90
CPU Address
2n + 0
2n + 0
2n + 1
2n + 1
2n + 0
2n + 1
2n + 0
2n + 1
2n + 2
2n + 1
2n + 2
2n + 0
2n + 1
2n + 2
2n + 3
2n + 0
2n + 2
2n + 1
2n + 2
2n + 3
2n + 4
2n + 1
2n + 2
2n + 4
D15 to D8
b31 to b24
b23 to b16
b15 to b8
b15 to b8
b7 to b0
b7 to b0
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
CPU Data
D7 to D0
b23 to b16
b31 to b24
b23 to b16
b23 to b16
b31 to b24
b31 to b24
b15 to b8
b15 to b8
b15 to b8
b15 to b8
b15 to b8
b15 to b8
b7 to b0
b7 to b0
b7 to b0
b7 to b0
b7 to b0
b7 to b0
b7 to b0
b7 to b0
b7 to b0
xxxxx
xxxxx
xxxxx
TMP91C016
2008-02-20