HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 111

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.1
4.1.1
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times, in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4.1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
Priority
High
Low
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests are accepted at all times in program
Exception Handling Types and Priority
Overview
Exception Type
Reset
Trace *
Direct transition
Interrupt
Trap instruction
(TRAPA) *
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
Exception Types and Priority
1
3
Section 4 Exception Handling
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES pin, or
when the watchdog timer overflows. The CPU enters the reset
state when the RES pin is low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Starts when a direction transition occurs as the result of SLEEP
instruction execution.
handling ends, if an interrupt request has been issued *
Started by execution of a trap instruction (TRAPA)
Starts when execution of the current instruction or exception
Rev. 5.00 Jan 10, 2006 page 85 of 1042
Section 4 Exception Handling
REJ09B0275-0500
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