HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 597

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt
source settings and data settings must be made. Interrupt source settings are made in the mailbox
interrupt register (MBIMR) and interrupt mask register (IMR), while transmit data settings are
made by writing the necessary data from the arbitration field, control field, and data field,
described below, in the corresponding message control (MCx[1]–MCx[8]) and message data
(MDx[1]–MDx[8]).
The number of bytes in the data actually transmitted depends on the data length code (DLC) in the
control field. If a value exceeding the value set in DLC is set in the data field, only the number of
bytes set in DLC will actually be transmitted.
Message Transmission and Interrupts:
CPU interrupt source settings
Transmission acknowledge and transmission abort acknowledge interrupts can be masked for
individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR)
interrupts can be masked in the interrupt mask register (IMR).
Arbitration field setting
In the arbitration field, the 11-bit identifier (STD_ID0–STD_ID10) and RTR bit (standard
format) or 29-bit identifier (STD_ID0–STD_ID10, EXT_ID0–EXT_ID17) and IDE.RTR bit
(extended format) are set. The registers to be set are MCx[5]–MCx[8].
Control field setting
In the control field, the byte length of the data to be transmitted is set in DLC0–DLC3. The
register to be set is MCx[1].
Data field setting
In the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. The
registers to be set are MDx[1]–MDx[8].
Message transmission wait
If message transmission is to be performed after completion of the message control (MCx[1]–
MCx[8]) and message data (MDx[1]–MDx[8]) settings, transmission is started by setting the
corresponding mailbox transmit wait bit (TXPR1–TXPR15) to 1 in the transmit wait register
(TXPR). The following two transmission methods can be used:
a. Transmission order determined by message identifier priority
b. Transmission order determined by mailbox number priority
When a is selected, if a number of messages are designated as waiting for transmission (TXPR
= 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order:
Section 15 Controller Area Network (HCAN)
Rev. 5.00 Jan 10, 2006 page 571 of 1042
REJ09B0275-0500