HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 512

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 486 of 1042
REJ09B0275-0500
Reception
Receive operation should be stopped (by clearing RE to 0) before making a module stop mode,
software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR,
RDR, and SSR are reset. If a transition is made without stopping operation, the data being
received will be invalid.
To continue receiving without changing the reception mode after the relevant mode is cleared,
set RE to 1 before starting reception. To receive with a different receive mode, the procedure
must be started again from initialization.
Figure 13.26 shows a sample flowchart for mode transition during reception.
Figure 13.23 Sample Flowchart for Mode Transition during Transmission
Read TEND flag in SSR
<Start of transmission>
Transition to software
standby mode, etc.
standby mode, etc.
Exit from software
operating mode?
<Transmission>
Yes
Yes
Yes
transmitted?
Initialization
TEND = 1
Change
All data
TE = 0
[2]
No
No
No
TE = 1
[1]
[3]
[1] Data being transmitted is interrupted.
[2] If TIE and TEIE are set to 1, clear
[3] Includes module stop mode, watch
After exiting software standby mode,
etc., normal CPU transmission is
possible by setting TE to 1, reading
SSR, writing TDR, and clearing
TDRE to 0, but note that if the DTC
has been activated, the remaining
data in DTCRAM will be transmitted
when TE and TIE are set to 1.
them to 0 in the same way.
mode, subactive mode, and subsleep
mode.