HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 893

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

IRR—Interrupt Register
Overload frame/bus off recovery interrupt flag
0
1
IRR
Bit
Initial value
Read/Write
Note: * Can only be written with 1 for flag clearing.
[Clearing condition]
Writing 1
Overload frame transmission or recovery
from bus off state
[Setting conditions]
• Error active/passive state
• Bus off state
— When overload frame is transmitted
— When 11 recessive bits are received
128 times (REC
:
:
:
Bus off interrupt flag
0
1
R/(W)*
IRR7
15
[Clearing condition]
Writing 1
Bus off state caused by
transmit error
[Setting condition]
When TEC
0
128)
R/(W)*
IRR6
14
256
0
R/(W)*
IRR5
Error passive interrupt flag
13
0
0
1
[Clearing condition]
Writing 1
Error passive state caused by transmit/receive error
[Setting condition]
When TEC
Receive overload warning interrupt flag
0
1
R/(W)*
Transmit overload warning interrupt flag
[Clearing condition]
Writing 1
Error warning state caused by receive error
[Setting condition]
When REC
IRR4
0
1
12
0
[Clearing condition]
Writing 1
Error warning state caused by transmit error
[Setting condition]
When TEC
Remote frame request interrupt flag
0
1
128 or REC
H'F812
Rev. 5.00 Jan 10, 2006 page 867 of 1042
Receive message interrupt flag
[Clearing condition]
Clearing of all bits in RFPR (remote request
wait register) of mailbox for which receive interrupt
requests are enabled MBIMR
Remote frame received and stored in mailbox
[Setting conditions]
When remote frame reception is completed
When corresponding MBIMR = 0
0
1
R/(W)*
96
IRR3
11
[Clearing condition]
Clearing of all bits in RXPR (receive complete
register) of mailbox for which receive interrupt
requests are enabled MBIMR
Data frame or remote frame
received and stored in mailbox
[Setting conditions]
When data frame or remote frame
reception is completed
When corresponding MBIMR = 0
0
Reset interrupt flag
0
1 Hardware reset (HCAN module stop,
96
software standby)
[Setting condition]
When reset processing is completed after
a hardware reset (HCAN module stop,
software standby)
[Clearing condition]
Writing 1
128
Appendix B Internal I/O Register
IRR2
10
R
0
IRR1
R
9
0
REJ09B0275-0500
R/(W)*
IRR0
8
0
HCAN