HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 13

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.7
Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
5.6
Section 6 PC Break Controller (PBC)
6.1
6.2
Notes on Use of the Stack ................................................................................................. 95
Overview........................................................................................................................... 97
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 100
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources............................................................................................................... 106
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 112
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
Usage Notes ...................................................................................................................... 122
5.5.1
5.5.2
5.5.3
5.5.4
DTC Activation by Interrupt............................................................................................. 124
5.6.1
5.6.2
5.6.3
Overview........................................................................................................................... 127
6.1.1
6.1.2
6.1.3
Register Descriptions ........................................................................................................ 129
6.2.1
Features................................................................................................................ 97
Block Diagram ..................................................................................................... 98
Pin Configuration................................................................................................. 99
Register Configuration......................................................................................... 99
System Control Register (SYSCR) ...................................................................... 100
Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM)........................... 101
IRQ Enable Register (IER) .................................................................................. 103
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 104
IRQ Status Register (ISR).................................................................................... 105
External Interrupts ............................................................................................... 106
Internal Interrupts................................................................................................. 108
Interrupt Exception Handling Vector Table......................................................... 108
Interrupt Control Modes and Interrupt Operation ................................................ 112
Interrupt Control Mode 0 ..................................................................................... 116
Interrupt Control Mode 2 ..................................................................................... 118
Interrupt Exception Handling Sequence .............................................................. 120
Interrupt Response Times .................................................................................... 121
Contention between Interrupt Generation and Disabling..................................... 122
Instructions that Disable Interrupts ...................................................................... 123
Times when Interrupts are Disabled .................................................................... 123
Interrupts during Execution of EEPMOV Instruction.......................................... 124
Overview.............................................................................................................. 124
Block Diagram ..................................................................................................... 125
Operation ............................................................................................................. 125
Features................................................................................................................ 127
Block Diagram ..................................................................................................... 128
Register Configuration......................................................................................... 129
Break Address Register A (BARA) ..................................................................... 129
.......................................................................................... 97
........................................................................... 127
Rev. 5.00 Jan 10, 2006 page xi of xxiv