HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 592

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 Controller Area Network (HCAN)
These constraints allow the setting range shown in table 15.4 for TSEG1 and TSEG2 in BCR.
Table 15.4 Setting Range for TSEG1 and TSEG2 in BCR
Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1.
Mailbox Transmit/Receive Settings: HCAN0, 1 each have 16 mailboxes. Mailbox 0 is receive-
only, while mailboxes 1 to 15 can be set for transmission or reception. Mailboxes that can be set
for transmission or reception must be designated either for transmission use or for reception use
before communication begins. The Initial status of mailboxes 1 to 15 is for transmission (while
mailbox 0 is for reception only). Mailbox transmit/receive settings are not initialized by a software
reset.
Rev. 5.00 Jan 10, 2006 page 566 of 1042
REJ09B0275-0500
(BCR [11:8])
Setting for transmission
Transmit mailbox setting (mailboxes 1 to 15)
Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding
mailbox for transmission use. After a reset, mailboxes are initialized for transmission use, so
this setting is not necessary.
Setting for reception
Transmit/receive mailbox setting (mailboxes 1 to 15)
TSEG1
* Setting is enabled except when BRP [13:8] = B'000000.
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Yes *
Yes *
Yes *
Yes *
Yes *
Yes *
Yes *
Yes *
Yes *
Yes *
Yes *
Yes *
001
No
010
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
011
No
TSEG2 (BCR [14:12])
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
100
No
No
101
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
110
No
No
No
No
111
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No