HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 590

IC H8S MCU FLASH 256K 100-QFP

HD64F2623FA20J

Manufacturer Part Number
HD64F2623FA20J
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2623FA20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 15 Controller Area Network (HCAN)
Table 15.3 BCR Register Value Setting Ranges
Name
Time segment 1
Time segment 2
Baud rate prescaler
Sample point
Re-synchronization jump width
b. Value Setting Ranges
The following formula is used to calculate the baud rate.
Example: With a 1 Mb/s baud rate and a 20 MHz input clock:
Rev. 5.00 Jan 10, 2006 page 564 of 1042
REJ09B0275-0500
The bit width consists of the total of the settable Time Quanta (TQ). TQ (number of system
clocks) is determined by the baud rate prescaler (BRP).
The value of SJW is stipulated in the CAN specifications.
The minimum value of TSEG1 is stipulated in the CAN specifications.
The minimum value of TSEG2 is stipulated in the CAN specifications.
TQ =
3
TSEG1
TSEG2
Bit rate [b/s] =
1 Mb/s =
Note: f
SJW
2
The BCR values are used for BRP, TSEG1, and TSEG2.
CLK
TSEG2
SJW
2
(BRP + 1)
0
=
f
CLK
(0 + 1)
(system clock)
2
20 MHz
(BRP + 1)
(3 + 4 + 3)
TSEG1
TSEG2
BRP
SAM
SJW
Abbreviation
(3 + TSEG1 + TSEG2)
f
CLK
B'0
Min. Value
B'0000
B'000
B'000000
B'00
Max. Value
B'1111
B'111
B'111111
B'1
B'11

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