HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 747

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and
bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the
software standby mode, watch mode, and when making a direct transition.
Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to.
21B.2.2 System Clock Control Register (SCKCR)
SCKCR is an 8-bit readable/writable register that performs clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7— Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,
this bit controls output. See section 21B.12, Clock Output Disabling Function, for details.
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Bit 3
OPE
0
1
Bit 7
PSTOP
0
1
Bit
Initial value :
R/W
High-Speed Mode,
Medium-Speed Mode,
Sub-Active Mode
Fixed high
Description
In software standby mode, watch mode, and when making a direct transition, address
bus and bus control signals are high-impedance.
In software standby mode, watch mode, and when making a direct transition, the
output state of the address bus and bus control signals is retained.
output (initial value)
:
:
PSTOP
R/W
7
0
—
—
6
0
Sleep Mode,
Sub-Sleep Mode
Fixed high
output
—
—
5
0
Section 21B Power-Down Modes [H8S/2626 Group]
Description
—
—
4
0
Rev. 5.00 Jan 10, 2006 page 721 of 1042
Software Standby
Mode, Watch Mode,
Direct Transition
Fixed high
Fixed high
STCS
R/W
3
0
SCK2
R/W
2
0
Hardware
Standby Mode
High impedance
High impedance
REJ09B0275-0500
SCK1
R/W
1
0
(Initial value)
SCK0
R/W
0
0