HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 612

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 Controller Area Network (HCAN)
3. Interrupts
4. Error counters
5. Register access
6. HCAN medium-speed mode
7. Register retention during standby
8. Using bit operation instructions
9. HTxD pin output in error passive state
10. Transition to HCAN sleep mode
Rev. 5.00 Jan 10, 2006 page 586 of 1042
REJ09B0275-0500
release. Also note that the reset status bit (GSR3) in the general status register (GSR) is set in
sleep mode.
When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8.2.1) is
not set by reception completion, transmission completion, or transmission cancellation for the
set mailboxes.
In the case of error active and error passive, REC and TEC normally count up and down. In the
bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96
during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set.
Byte or word access can be used on all HCAN registers. Longword access cannot be used.
HCAN registers cannot be read or written to in medium-speed mode.
All HCAN registers are initialized in hardware standby mode and software standby mode.
Start flags in HCAN are cleared by writing 1 to them; there is no need to use bit operation
instructions to clear them. To clear a flag, use the MOV instruction to write a 1 to the bit to be
cleared.
If the HRxD pin becomes fixed at 1 during message transmission or reception when the HCAN
is in the error active state, the HTxD pin will output 0 continuously while in the error passive
state. To stop continuous 0 output to the CAN bus, disable the HCAN by means of an error
warning interrupt or by setting the HCAN module stop mode through detection of a fixed 1
state by the HxRD pin monitor.
The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0 immediately after
an HCAN sleep mode transition effected by setting TXPR of the HCAN to 1 and setting
MCR5 to 1. When a transition is made to the HCAN sleep mode by means of the above steps,
a 10-cycle wait should be inserted after the TxPR setting. After an HCAN sleep mode
transition, release the HCAN sleep mode by clearing MCR5 to 0.