HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 628

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 16 A/D Converter
16.4.2
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the
first channel in the group (AN0). When two or more channels are selected, after conversion of the
first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion
continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion
results are transferred for storage into the ADDR registers corresponding to the channels.
When the operating mode or analog input channel must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1 to start A/D conversion again from the first
channel (AN0). The ADST bit can be set at the same time as the operating mode or input channel
is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
next. Figure 16.4 shows a timing diagram for this example.
[1] Scan mode is selected (SCAN = 1), channel set 0 is selected (CH3 = 0), scan group 0 is
[2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to
[3] Conversion proceeds in the same way through the third channel (AN2).
[4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set
[5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is
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selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and
A/D conversion is started (ADST = 1)
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this
time, an ADI interrupt is requested after A/D conversion ends.
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
Scan Mode (SCAN = 1)