HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 18

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.6 Operation Timing.............................................................................................................. 354
10.7 Usage Notes ...................................................................................................................... 362
Section 11 Programmable Pulse Generator (PPG)
11.1 Overview........................................................................................................................... 373
11.2 Register Descriptions ........................................................................................................ 377
11.3 Operation .......................................................................................................................... 387
11.4 Usage Notes ...................................................................................................................... 396
Section 12 Watchdog Timer
12.1 Overview........................................................................................................................... 399
12.2 Register Descriptions ........................................................................................................ 403
Rev. 5.00 Jan 10, 2006 page xvi of xxiv
10.6.1 Input/Output Timing ............................................................................................ 354
10.6.2 Interrupt Signal Timing........................................................................................ 358
11.1.1 Features................................................................................................................ 373
11.1.2 Block Diagram ..................................................................................................... 374
11.1.3 Pin Configuration................................................................................................. 375
11.1.4 Registers............................................................................................................... 376
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 377
11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 378
11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 379
11.2.4 Notes on NDR Access.......................................................................................... 379
11.2.5 PPG Output Control Register (PCR).................................................................... 381
11.2.6 PPG Output Mode Register (PMR)...................................................................... 383
11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 385
11.2.8 Module Stop Control Register A (MSTPCRA) ................................................... 386
11.3.1 Overview.............................................................................................................. 387
11.3.2 Output Timing...................................................................................................... 388
11.3.3 Normal Pulse Output............................................................................................ 389
11.3.4 Non-Overlapping Pulse Output............................................................................ 391
11.3.5 Inverted Pulse Output .......................................................................................... 394
11.3.6 Pulse Output Triggered by Input Capture ............................................................ 395
12.1.1 Features................................................................................................................ 399
12.1.2 Block Diagram ..................................................................................................... 400
12.1.3 Pin Configuration................................................................................................. 402
12.1.4 Register Configuration......................................................................................... 402
12.2.1 Timer Counter (TCNT)........................................................................................ 403
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 404
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 408
12.2.4 Pin Function Control Register (PFCR) ................................................................ 410
12.2.5 Notes on Register Access..................................................................................... 410
............................................................................................. 399
.................................................... 373